Floorplanning is a crucial phase in VLSI physical design, complicated by constraints such as fixed outlines, whitespace removal, and pre-placed modules. Traditional floorplanners often neglect the impact of pin assignment on subsequent stages like detailed placement and routing, which can degrade overall design performance. Piano addresses this gap by simultaneously optimizing module placement and pin assignment under multiple constraints. It constructs a graph representing geometric relationships and netlist connections among modules, then iteratively searches for shortest paths to assign pins effectively. This graph-based approach allows accurate evaluation of feedthrough and unplaced pins, guiding improvements in layout quality. To further enhance the design, Piano incorporates a whitespace removal strategy and applies three local optimizers to refine layout metrics in multi-constraint scenarios. Experimental results on benchmark circuits demonstrate that Piano achieves an average 6.81% reduction in half-perimeter wirelength (HPWL), a 13.39% decrease in feedthrough wirelength, a 16.36% reduction in feedthrough modules, and a 21.21% drop in unplaced pins, all while maintaining zero whitespace. These improvements suggest that integrating pin assignment awareness into floorplanning can substantially benefit VLSI physical design. The framework offers a promising direction for future floorplanning tools to handle complex constraints more effectively and improve downstream design stages. Adopting such methods can lead to better layout quality, reduced routing complexity, and potentially enhanced chip performance.
👉 Pročitaj original: arXiv AI Papers
