In modern VLSI circuit design, the RTL stage is pivotal for timing optimization to ensure system reliability and performance. Timing violations at this stage can lead to functional failures or system crashes, making early detection and repair essential. Traditional timing optimization methods rely heavily on manual expertise, which is time-consuming and iterative. ViTAD addresses this challenge by automating the debugging process through a combination of parsing Verilog code and timing reports to build a Signal Timing Dependency Graph (STDG). This graph enables detailed violation path analysis, which is then used alongside large language models to infer the root causes of timing violations. By leveraging a domain-specific knowledge base, ViTAD generates customized repair solutions tailored to the identified issues. The method was evaluated on a dataset of 54 real-world timing violation cases from open-source projects, demonstrating a 73.68% success rate in repairs. This represents a 19.30% improvement over a baseline approach that uses only LLMs, which achieved a 54.38% success rate. The results highlight ViTAD’s effectiveness in automating and improving the debugging process for RTL timing violations. This approach reduces reliance on manual expertise, accelerates the design cycle, and enhances the reliability of VLSI systems. Future work could explore expanding the knowledge base and refining the integration with LLMs to further boost repair accuracy and coverage.
👉 Pročitaj original: arXiv AI Papers
